Signal propagation delay is a significant factor in high performance VLSI design. Signal propagation delay not only slows performance of an Integrated Circuit (xe2x80x9cICxe2x80x9d), but if the signal propagation delay exceeds the period of an IC clock, the IC will simply not function properly. Similarly, signal transition time is another significant factor in high performance VLSI design. A transition time that is too long permits noise to couple into the signal, which can cause spurious transitions of the signal in downstream circuitry, which may also cause functional errors or failures.
Signal propagation delay is primarily due to resistive-capacitive (xe2x80x9cRCxe2x80x9d) delay of the metal interconnects between circuit elements of the IC design. In general, signal propagation delay increases geometrically as a function of interconnect length. The resistive and capacitive components of the interconnect also affect transition time of the signal being propagated. It is desirable to keep the transition time below a specified maximum on all of the interconnects. IC designers address the issue of signal propagation delay and signal transition time using strategic placement of repeaters. Too many repeaters, however, consume space on the IC without improving the IC performance. It is important, therefore, to position repeaters only where they are beneficial to the overall design.
Certain constraints in IC design present a challenge to the repeater insertion process. Because optimum repeater insertion for RC delay is a function of interconnect length, repeater placement options are limited. The space on the IC design for optimal repeater insertions for any one interconnect may already be populated by another optimally placed repeater or the IC circuit design itself. In this case, the repeater may be placed in a different and sub-optimal position or the circuit element or repeater already populating the optimum space may be moved elsewhere. As one of ordinary skill in the art appreciates, this proposed shifting of repeaters or circuit elements has an impact on the performance of the overall IC design. Accordingly, repeater placement involves a number of trade-offs in view of the competing objectives. The competing objectives are minimizing interconnect RC delay and obtaining a target transition time while limiting the impact of the additional repeaters on IC space and power.
A known repeater insertion method comprises executing interconnect routing software for a plurality of interconnecting functional blocks. In the known method, an automatic repeater insertion process executes and attempts to position repeater elements at optimum spaces along the interconnects. Unfortunately, the optimum placement of the repeater elements is often directly over one of the functional blocks. The IC designer then assesses the result and manually identifies offending repeaters and repositions them for each interconnect or removes them entirely. As one of ordinary skill in the art appreciates, such a manual assessment, identification and repeater placement or removal process is time consuming and, therefore, expensive, and may not always result in an optimum IC design. Once the repeaters are moved, it is also known to group the repeaters. Disadvantageously, this grouping step can cause the repeaters to be positioned too close or too far from each other.
There is a need, therefore, for an improved process of repeater placement in an IC design and a system for implementing the improved process.